Current Sensing Analog PLL Oscillator for digital theremin

Current Sensing Theremint Oscillator With PLL and Differential Full Quadrant Sine Output

Yet another attempt to design the best theremin oscillator ever, with PLL and current sensing.

- VCO is based on State Variable Filter with fully differential integrators.

- Full quadrant 0.5Vpp 1V differential voltage VCO outputs, allows to synthesize any other phases.

- Pure sine waveform 3Vpp drive signal for LC tank (less than -70dB harmonics)

- 4.5V power supply (draws about 20mA when driving LC tank with 10mA current)

- Stable amplitude for wide range of output frequencies (100KHz .. 2MHz)

I believe, it should be practically usable as a front-end for digital theremins.

LTSpice model to play with is available on GitHub (clone repository and open theremin_oscillator_bjt_pll_v01.asc)

The schematic is expected to be cheap, with PCB manufacturing and assembly using JLCPCB.

* about 60 BJTs, most of them should be matching pairs

* LMH6642 is used as LC tank drive buffer, can provide up to 75mA current, with close to R/R output voltage.

* MCP6121 is used as Control Voltage buffer

Simulation screenshots:

Antenna voltage and inductor current

Control voltage

Antenna voltage and inductor current when locked

Drive signal voltage and current when locked

https://github.com/fpga-theremin/sensors/raw/main/models/ltspice/theremin_oscillator_bjt_analog_pll/images/theremin_oscillator_bjt_pll_sim_drive_voltage_and_current_locked.png

Drive signal FFT in locked state

VCO differential output

A theremin designer’s nightmare.

Happy New Year, everyone!
May your circuits be simple!”

A theremin designer’s nightmare.
-- ILYA

Agree. Probably, it's an over-engineering.
I'm trying to simplify VCO, to use just a single LM13700 + 2 opamps + a few BJTs.

Simplified LM13700 based SVF VCO

* Simplified LM13700 based voltage controlled oscillator.

* Still provides full quadrant output (two sine signals shifted by 90 degrees), but not differential as in previous case.

* Opamps used in VCO may drive LC tank directly with close to rails amplitude (0.2V minimal offset from rails is recommended).

LTSpice model: ota_svf_vco_v01.asc - clone from GitHub for experiments

- Stable amplitude at frequency range 200KHz-2MHz

- Single LM13700, two LMH6642 (or single LMH6643), 4 BJTs.

- Working range may be adjusted by R10, R20 to cover the desired frequency range

- R18 controls amplitude of the output signals, while R17 is responsible for keeping the amplitude constant for the range of frequencies

- R14, R12 provide fine-tuning for input bias, should be tuned to keep the same zero point of both VCO outputs.

Simulation results

Output signal amplitude in wide frequency range (sweep 400KHz to 1600KHz)

Zoom in of VCO output signals

Resonance visible in antenna voltage and inductor current while drive frequency is crossing LC resonant frequency

Consumed current from power lines

Simplified LM13700 PLL based Theremin Sensor

Adding phase detector on LM13700 OTA.

I believe, this version is practically usable, and not a nightmare of theremin designer anymore.

There are 4 different square outputs added. Does it make sense to use differential LVDS driver on output - to minimize noise of transmission lines?

LTSpice model on github 

Simulation results

Antenna voltage

Control Voltage and inductor current - PLL locking process

Drive signal voltage and inductor current - when locked

Drive signal spectrum

VCO outputs - two sines with 90 degrees phase shift

Square outputs - 4 different phases

I'm looking for options for high-end but cheap enough theremin sensor design. Cheap MCU instead of more expensive and harder to program FPGA is one of options.
RP2354A, RP2354B are as low as $1.45/$1.6 on JLCPCB, have internal 2MB flash, and require minimum of external components. Since it's so inexpensive, even may be put on each sensor,
to handle purely measuring, averaging and calculating one axis value, and sending it to main MCU.
RP2354B can be chosen not because of more pins, but because of better heat dissipation - important if you want to overclock it. 300-400MHz can be easy achieved.
As reported, even works at 600MHz sys_clk.

PIO state machines have very limited programming capabilities, but at least may detect input pin edges with sys_clk precision (e.g. 400MHz) by two PIO state machiines working together.
Using this approach it will send cycle counter value which is decrementing each clock cycle if signal edge is detected to DMA channel, for further processing by CPU side.
This is useful if you need to measure frequency of the oscillator by calculation of distance between N signal periods. 400MHz precision is already area of FPGA.

Another solution, if sensor is based on oscillator with full quadrant output - sin(x) and cos(x) - sample two outputs synchronously using ADC and calculate current phase using ATAN2.
It gives much more information about signal phase than single pin zero-crossing detection - instead of collecting zero crossing position with higher precision (400MHz) but only twice per signal period,
we may get phase of oscillation at lower sample rate, but extract a lot of phase information from every sample.

E.g. cheap dual channel ADC like HT9201 ($3.23) sampling at 20MHz, gives 20 phase values with 8-10 bits precision with a minimal noise. PIO will read sin and cos values and push to DMA circular buffer.
One CPU core will read data from buffer, convert to phase using ATAN2 lookup table, append cycle counter to the phase when it wraps 2*PI, and do some averaging by calculating difference between current phase value and one delayed by N cycles.
This CPU will have only 10-20 clock cycles per ADC sample, so most of the work has to be done by the second CPU core.
Even during one oscillator clock cycle of 1MHz this method could collect 12-14 bits of phase data. Taking difference between current sample and value delayed by one audio sample (~400 samples step) gives at least 8 additional bits.

Simple phase difference between value calculated from one sample and value sampled 400 ADC cycles ago gives 16-18 clean bits of oscillator frequency information. Averaging during one audio sample period should provide at least 24 meaningful bits
of oscillator frequency/period value with only 1 audio sample latency. Averaging using 1KHz time window would give 29-30 bits of precisely measured frequency value with 0.5ms latency, which is actually an overkill.
This 2-channel ADC based solution assumes that there is a pretty sensitive theremin sensor providing SIN+COS output, based on analog PLL and current sensing.
Total cost for the sensor board can be $10 .. $15 based on my estimations. Interface with the synthesizer part could be I2S for axis value providing updated interpolated value for each audio sample in a realtime (e.g. could provide ready-to-use pitch phase or volume multiplier),
and SPI for changing of sensor settings (like calibration parameters and options for conversion of the measured frequency to axis value - pitch frequency or phase and volume).